用VHDL语言编写程序

发布网友 发布时间：2022-04-24 12:16

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热心网友 时间：2023-10-12 13:25

我用quartusⅡ已编译并且仿真都对的，我写的是0亮1灭，如果实际情况与这相反，你自己倒一下。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
USE IEEE.numeric_std.all;

ENTITY test IS
PORT (clock: in std_logic; -----clock1加48MHz的信号
row: out std_logic_vector(0 to 7));
END test;

ARCHITECTURE behave OF test IS

CONSTANT fp_clka:INTEGER:=12000000; ---扫描信号频率为2Hz
SIGNAL a: INTEGER RANGE 0 TO 12000001;
signal saomiao :integer range 0 to 9;
SIGNAL clka: std_logic;

BEGIN
PROCESS (clock)
BEGIN
IF rising_edge(clock) THEN
IF a<fp_clka then --clka
a<=a+1;
clka<=clka;
ELSE
a<=0;
clka<= NOT clka;
end if;
end if;
end process;

process(clka)
BEGIN
IF rising_edge(clka) THEN
saomiao<=saomiao+1;
if saomiao=9 then
saomiao<=0;
end if;
case saomiao is ---'1'代表不亮,'0'代表亮
when 0 =>row<="01111111";
when 1 =>row<="10111111";
when 2 =>row<="11011111";
when 3 =>row<="11101111";
when 4 =>row<="11110111";
when 5 =>row<="11111011";
when 6 =>row<="11111101";
when 7 =>row<="11111110";
when 8 =>row<="00000000";
when others =>row<="11111111";
END CASE;
END IF;
end process;
END behave;

热心网友 时间：2023-10-12 13:26

请问下灯是0亮还是1亮，引脚配置需要你自己弄下了。
若为1亮则有：

library ieee;
use ieee.std_logic_11.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity LEDcontrol is ----定义实体名为 LEDcontrol

port(

CLK :in std_logic; ----输入时钟

LED8 :out std_logic_vector(7 downto 0)----8位输出

);

end entity LEDcontrol;

architecture LEDC of LEDcontrol is

signal n :integer range 0 to 23999999;---------24000000 分频
signal m :integer range 0 to 9;

signal C500ms :std_logic;-------内0.5s时钟

begin
------------------------------------------------------------------------------------------------------------
CLK_500ms:process(CLK) ---- 输入时钟分频
begin

if CLK'event and CLK='1' then

if n<12000000 then
n<=n+1;
CP1ms<='0'; ---- 低电平持续0.25s
elsif n<23999999 then
n<=n+1;
CP1ms<='1'; ---- 高电平持续0.25s
else
n<=0;
end if;

end if;

end process CLK_500ms;
------------------------------------------------------------------------------------------------------------

------------------------------------------------------------------------------------------------------------
LED_CON:process(C500ms) ---- 点灯控制
begin

if C500ms'event and C500ms='1' then

if m<9 then

if m=0 then
LED8 <= "00000001"; ----0亮的话改成"11111110"就可以了,以下类似
m <= m + 1;

elsif m=1 then
LED8 <= "00000010";
m <= m + 1;

elsif m=2 then
LED8 <= "00000100";
m <= m + 1;

elsif m=3 then
LED8 <= "00001000";
m <= m + 1;

elsif m=4 then
LED8 <= "00010000";
m <= m + 1;

elsif m=5 then
LED8 <= "00100000";
m <= m + 1;

elsif m=6 then
LED8 <= "01000000";
m <= m + 1;

elsif m=7 then
LED8 <= "10000000";
m <= m + 1;

elsif m=8 then
LED8 <= "11111111";
m <= m + 1;
else
LED8 <= "00000000";
m <= 0;

end if;

end if;

end process LED_CON;
------------------------------------------------------------------------------------------------------------

end LEDC;

热心网友 时间：2023-10-12 13:26

我用quartusⅡ已编译并且仿真都对的，我写的是0亮1灭，如果实际情况与这相反，你自己倒一下。
LIBRARY
IEEE;
USE
IEEE.STD_LOGIC_11.ALL;
USE
IEEE.STD_LOGIC_SIGNED.ALL;
USE
IEEE.numeric_std.all;
ENTITY
test
IS
PORT
(clock:
in
std_logic;
-----clock1加48MHz的信号
row:
out
std_logic_vector(0
to
7));
END
test;
ARCHITECTURE
behave
OF
test
IS
CONSTANT
fp_clka:INTEGER:=12000000;
---扫描信号频率为2Hz
SIGNAL
a:
INTEGER
RANGE
0
TO
12000001;
signal
saomiao
:integer
range
0
to
9;
SIGNAL
clka:
std_logic;
BEGIN
PROCESS
(clock)
BEGIN
IF
rising_edge(clock)
THEN
IF
a<fp_clka
then
--clka
a<=a+1;
clka<=clka;
ELSE
a<=0;
clka<=
NOT
clka;
end
if;
end
if;
end
process;
process(clka)
BEGIN
IF
rising_edge(clka)
THEN
saomiao<=saomiao+1;
if
saomiao=9
then
saomiao<=0;
end
if;
case
saomiao
is
---'1'代表不亮,'0'代表亮
when
0
=>row<="01111111";
when
1
=>row<="10111111";
when
2
=>row<="11011111";
when
3
=>row<="11101111";
when
4
=>row<="11110111";
when
5
=>row<="11111011";
when
6
=>row<="11111101";
when
7
=>row<="11111110";
when
8
=>row<="00000000";
when
others
=>row<="11111111";
END
CASE;
END
IF;
end
process;
END
behave;